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所在平台: Udemy |
课程主页: https://www.udemy.com/course/cracking-programming-questions-digital-vlsi-dv-interviews/
课程评论：没有评论
课程名称：破解编程问题（数字VLSI DV面试） 课程概述： 随着数字VLSI设计趋向于复杂的SOC设计，设计验证工作正日益向软件导向转变。设计和验证工程师需要具备强大的硬件和软件技能，尤其是在硬件与软件接口方面。随着验证测试平台和仿真模型变得愈加复杂，软件编程知识已成为任何验证工程师的必备技能。一名设计验证工程师应深入掌握至少一种编程语言（如C/C++/SystemVerilog），具备强大的脚本编写能力，熟悉UNIX/Linux环境，并理解面向对象编程的概念。 因此，测试候选人编程基础理解的问题出现在几乎所有验证工作面试中。思考和编写算法、建模设计行为是面试的关键组成部分。硬件描述语言（HDL）用于独立于任何底层实现技术建模数字逻辑电路的行为。VHDL和Verilog是数字逻辑设计中使用的两种流行的HDL，而近年来，SystemVerilog（作为Verilog的超集）因支持面向对象编程概念及其他在验证设计中非常有用的特性而变得更为广泛应用。 因此，本课程（实践测试）组织了六个时间限制的试卷，涵盖了180多道常见面试题及其答案。针对的主题包括基础编程概念、面向对象编程概念、UNIX、Linux、C、C++、PERL、Verilog和SystemVerilog基础。 免责声明： 课程尽力确保实践测试的完整性和准确性，但不提供任何保证。作者对因本实践测试或其他相关资源中的信息引起的任何损失或损害不承担责任。这些实践测试为作者的独立工作，未得到他们雇主的认可。
In the present day scenario where Digital VLSI Designs are trending towards SOC designs with increased complexity, the Design Verification job is visibly becoming more and more software oriented. Both Design and Verification Engineers need to possess strong hardware and software skills surrounding the hardware and software interface. Additionally, with verification testbenches and simulation models becoming more and more complex, software programming knowledge has become a must-have skill for any Verification Engineer. A Design Verification Engineer should know at-least one programming language thoroughly (C/C++/SystemVerilog), should have strong scripting skills, working knowledge and familiarity with UNIX/Linux environments, and a good understanding of object oriented programming concepts. Due to these reasons, questions that test a candidate's understanding of programming basics are part of almost all Verification job interviews. Ability to think and code algorithms, and model design behaviors forms a vital component of an interview. Hardware Description Languages (HDL) are used to model behavior of digital logic circuits independently of any underlying implementation technology. VHDL and Verilog were the two popular HDLs used for digital logic design, and in the recent years SystemVerilog (which is a super set of Verilog) has become more widely adopted as it supports object oriented programming concepts and several other features which are very useful for implementing testbenches that are used to verify designs. This course (practice tests) is therefore organized into six time bound test papers covering some of the most commonly asked interview questions (180+ questions) with their answers. Targeted topics include Basic Programming concepts, Object Oriented Programming concepts, UNIX, Linux, C, C++, PERL, Verilog, and SystemVerilog(Basics).DisclaimerEvery effort has been made to make these practice tests as complete and as accurate as possible, but no warranty is implied. The authors shall have neither the liability nor the responsibility to any person or entity with respect to any loss or damages arising from the information contained in these practice tests or other resources accompanying these tests. These practice tests are independent work of the authors and are not endorsed by their employers.
