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所在平台: Udemy |
课程主页: https://www.udemy.com/course/complete-training-design-uart-using-verilog-or-vhdl-on-fpga/
课程评论：没有评论
课程名称：基于VERILOG/VHDL的FPGA UART设计指导项目教程 课程概述：本课程是一门实用课程，旨在教你如何使用Verilog HDL编程语言在FPGA上设计你的第一个UART项目。你将学习全双工UART传输和半双工传输之间的区别及其技术差异。课程中将介绍如何使用LOGISM EDA工具设计、测试和模拟逻辑电路。你将了解波特钟的概念，学习如何从系统时钟合成波特钟以及如何计算生成频率。此外，你将知道波特率的意义，了解标准波特率及如何从系统时钟生成这些波特率。课程还将教你如何设计和连接接收器和发射器与其波特钟，并将其组合成收发器。课程分为三个部分：接收器、波特发生器和发射器。这门课程包含17个视频，每个模块教授设计的特定部分，使用大量的视觉效果、箭头和图片使教程易于理解。建议在观看教程时使用LOGISM电路文件以便更好地理解。你将在第二节课附带VHDL脚本和LOGISM电路，不需要任何硬件，仅需电脑即可。课程内容简洁明了，直截了当。
This is a practical course, that will teach you how to design your first UART project on FPGA using Verilog HDL programming language.In this course, you will learn the difference between a full duplex UART transmission and a half-duplex transmission including their technical difference. You will how to use LOGISM EDA tool to design, test and simulate logic circuits. You will a baud clock, learn how it is synthesized from system clock and how to calculate the frequency of generation.you will learn what a baud rate means and also learn the standard baud rates and how to generate them from the system clock. You will learn how to design and wire the receiver and transmitter to their baud clocks and how they are joined together to make up the transceiver.The course is divided into three sections: the receiver, the baud generator and transmitter.This a 17 video course. each module teaching about a particular part of the design.a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.kindly use the logism circuit file while watching the tutorial for easy understanding. You will get the VHDL scripts and the logism circuit attached to lesson two. No hardware is required just your pc.It was kept brief and straight to the point.
