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所在平台: Udemy |
课程主页: https://www.udemy.com/course/complete-systemverilog-for-rtl-verification-part-1/
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课程名称：验证系列第一部分：SystemVerilog基础 课程概述：在VLSI（超大规模集成电路）行业中，主要分为设计系统和验证系统两个分支。Verilog和VHDL是大多数设计工程师在这一领域中的热门选择。然而，虽然初步的功能验证可以使用硬件描述语言（HDL）进行，但HDL在代码覆盖分析、边界情况测试等方面的能力有限，有时甚至无法完成这些检查。因此，专门的验证语言如SystemVerilog开始成为设计验证的主要选择。SystemVerilog的面向对象特性带来了继承、多态性等功能，增加了发现设计中关键错误的能力，这是HDL无法做到的。与数字系统设计相比，验证过程显得更加复杂且有趣，因此需要大量的面向对象构造，而不仅仅局限于Verilog。SystemVerilog已成为数字系统验证工程师中最受欢迎的选择之一。本课程将带您了解编写SystemVerilog测试平台和进行芯片验证的常用技术。课程结构设计合理，旨在帮助任何希望学习SystemVerilog的人能够理解相关内容。最后，实践是成为专家的关键。
VLSI Industry is divided into two popular branches viz. Design of System and Verification of the System. Verilog, VHDL remain the popular choices for most Design Engineers working in this domain. Although, preliminary functional verification can be carried out with Hardware Description Language. Hardware Description language possesses limited capabilities to perform code coverage analysis, Corner cases testing, etc and in fact sometimes it becomes impossible to perform this check with HDL's. Hence Specialized Verification languages such as SystemVerilog start to become the primary choice for the verification of the design. The SystemVerilog Object-oriented nature allows features such as Inheritance, Polymorphism, etc. adds capabilities of finding critical bugs inside design that HDL simply cannot find. Verification is certainly more tricky and interesting as compared to designing a digital system and hence it consists of a large number of OOP's Constructs as opposed to Verilog. SystemVerilog is one of the most popular choices among Verification Engineer for Digital System Verification. This Journey will take you to the most common techniques used to write SystemVerilog Testbench and perform Verification of the Chips. The course is structured so that anyone who wishes to learn about System Verilog will able to understand everything. Finally, Practice is the key to become an expert.
