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所在平台: Udemy |
课程主页: https://www.udemy.com/course/axi-infra-on-xilinx/
课程评论：没有评论
**课程名称：** 基于Xilinx FPGA IP和Verilog的AMBA AXI基础设施 **课程概述：** 本课程旨在深入解析AMBA AXI协议，解释其在现代SoC和复杂系统中的重要性。AXI是ARM标准总线，被Xilinx、Intel、AMD等所有硬件厂商广泛支持，并随着人工智能的发展，其应用将愈发普及。本课程将详细讲解AXI协议及其各个子协议，同时通过Xilinx Vivado平台，教授IP的使用、仿真方法等。 **目标学员：** * 使用AXI模块进行FPGA设计的工程师。 * 初次接触AXI协议的工程师。 * 寻求FPGA或SoC开发职位的研究生。 **课程内容：** 课程以“由浅入深”的方式，首先讲解AXI-Stream和AXI-Lite协议，并使用Verilog进行设计和仿真，帮助学员建立对AXI协议的直观理解。随后，课程将深入AXI通用协议，并结合Xilinx提供的AXI基础设施，重点关注仿真层面的应用，不涉及FPGA板级运行。课程还回顾了ARM的AXI规范，以帮助学员更好地阅读和理解官方文档。 **特别鸣谢：** 感谢ARM的Eduard Vardanyan提供的宝贵支持和专业知识，使得复杂AXI概念能够清晰地传达。 **注意事项：** * 课程代码已在Github上提供。 * 建议学员具备一定的Verilog和硬件基础。 * 讲师为非英语母语者，已尽力保证表达清晰，学生若遇到语法或发音问题，请多包涵。
Why AXI? ========= The answer is simple - there is NO any Soc or complex system, which does not contain AXI. If your work somehow is connected with processor, controller or any other big system than there will be multiple AXI buses in the system. AXI bus is a ARM standard bus, which is supported by all hardware companies e.g. Xilinx, Intel, AMD and so on. And by the advance of AI the AXI is going to be more and more popular.In this course AXI protocol and its sub-parts will be explained. Also as a free side knowledge you will study Vivado with its IPs, simulation methods and many more.Target Students==============The course is mainly targeted for FPGA designers, who are using AXI based modules in the design. Also the course will be useful for engineers who is starting to use AXI protocol.The course is extremely helpful for graduate students who is looking for a new job as a FPGA or Soc Developer, in my previous 3 companies AXI questions were the most often to ask the fresh graduates for hire.Course Content==============In the course mainly the basics of AXI protocol family is explained, which allows students easily understand and use AXI based IPs. This is more practical view of AXI usage allowing for jump start to use AXI based modules. The course does not go to FPGA board level,as the target is AXI protocol and Xilinx provided AXI Infrastucture understanding.The course concentrated on simulation level, not FPGA board running is done.The AXI protocol is complex enough and sometimes it takes much time to get used to it. Usually the AXI protocol is easy to understand when you are familiar with much easy version of it, which are AXI-Stream and AXI-Lite. The course is based on bottom-up-style. At first I explain AXI-stream protocol, than explain AXI-Lite protocol in detail. We do both of these protocol designs using Verilog. Than having all that baggage of knowledge we move to AXI protocol. In the course I tried to review the ARM speck for AXI, hoping that this will help students easily jump in speck reading, after finishing the course.Special Thanks:=============I want to express special thanks to Eduard Vardanyan, from ARM, for his great support in making this course. His profound experience and deep knowledge helped me to explain complex AXI parts simply. Without his help I could not do this. Caution:=======Also I apologize for my English, I tried my best to speak clearly and grammatically correct, however sometimes there are some mistakes. I really hope that my non-native English will not bother students to understand the material. Course Materials:===============All course codes can be downloaded from Github.Note: If you have software background, I would suggest little bit become familiar with Verilog. There are several lectures which require Verilog and hardware basics.
