VLSI Chip Design and Simulation with Electric VLSI EDA Tool

所在平台: Coursera

课程主页: https://www.coursera.org/learn/vlsi-chip-design-and-simulation-with-electric-vlsi-eda-tool

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课程简介

课程名称：VLSI芯片设计与模拟（使用Electric VLSI EDA工具） 课程概述：本课程深入探讨CMOS VLSI设计与模拟，涵盖集成电路技术、CMOS结构、历史发展、处理器复杂性、MOS晶体管设计、非理想特性、功耗、低功耗设计技术，以及CMOS逻辑门的实用见解。参与者将在“模拟电路CMOS芯片设计与模拟”模块中深入学习基本组件和电路设计，使用Electric VLSI EDA工具进行实践。 课程大纲： 1. **CMOS VLSI导论** - 该模块对CMOS结构和功能进行了全面介绍，探讨了集成电路技术的优势，以及IC技术的历史发展、摩尔定律和技术缩放。参与者将深入了解处理器的重要性以及从硅砂制造集成电路的过程，包括各个阶段。 - 探索MOS晶体管设计的复杂性，包括类型和操作模式，讨论理想与非理想晶体管特性及各种泄漏类型，环境变化和温度敏感性等影响晶体管性能的因素。 - 模块还涵盖CMOS晶体管设计、CMOS反相器设计及CMOS设计中的功耗、噪声裕度和传播延迟分析，强调功耗的机制与低功耗设计的优势。 - 包括动态电压与频率缩放（DVFS）、电源门控及减少短路功耗的策略等功耗减少技术，强调超低功耗电路设计和能效设计原则的优化。 2. **使用Electric VLSI EDA工具的模拟电路CMOS芯片设计与模拟** - 本模块使参与者沉浸于基本组件和电路的原理图和布局设计中，首先介绍基本的棒图（stick diagrams）及其设计规则和实例，随后讲解Electric VLSI EDA工具的安装和使用过程。 - 提供工具内置功能的全面概览，包括重要检查和波形模拟。此外，还覆盖了将LTspice与Electric VLSI EDA工具结合使用的内容，提升参与者的设计探索能力。 - 本模块还提供设计PMOS、NMOS、CMOS反相器、共源放大器、共漏放大器和三阶段振荡器等各种电路的原理图和布局表示的指导，确保参与者能实践设计、模拟以及3D可视化布局。 3. **使用Electric VLSI EDA工具的数字电路CMOS芯片设计与模拟** - 此模块旨在提供参与者对各种CMOS逻辑电路的原理图和布局设计的深入理解。指导参与者在预定义库中创建新单元，选择“原理图或布局”作为设计方法。 - 强调系统工作流程，每个设计从原理图单元开始，并在每一步进行设计规则检查（DRC）以评估表现层次。设计之后进行模拟，通过波形分析定义其特性。 - 参与者将掌握原理图电路的布局设计技能，在最终阶段实施DRC、电气规则检查（ERC）和网表与组件连接性检查（NCC），确保设计的可行性。模块特别涵盖AND门、OR门，以及它们的互补门、XOR门和半加器电路的设计，利用Electric VLSI EDA工具完成正特性的验证。 本课程不仅关注理论概念，还注重参与者在EDA工具使用方面的实践技能培养。

课程大纲

Name:Introduction to CMOS VLSI

Description:This module provides a thorough introduction to CMOS structures and functionality, exploring IC technology advantages. It covers the historical timeline of IC technology, Moore's Law, and technology scaling. Participants delve into the crucial role of processors and the intricate process of crafting Integrated Chips from Silica Sand, spanning various stages. The module explores MOS transistor design intricacies, covering types and operational modes. It discusses characteristics of ideal and non-ideal transistors, including diverse leakage types. Factors impacting transistor performance, like temperature sensitivity and environmental variations, are explored. The curriculum covers CMOS transistors design, CMOS inverter design, and analysis of power dissipation, noise margin, and propagation delay in CMOS designs, encompassing power dissipation aspects and mechanisms. The module investigates leakage current sources, low-power design benefits, and factors influencing power consumption. Power reduction techniques, including Dynamic Voltage and Frequency Scaling (DVFS), power gating, and strategies for mitigating short-circuit power consumption, are included. Emphasis is on ultra-low power circuit design, power reduction, and optimization techniques for a holistic understanding of energy-efficient design principles. The module concludes with an overview of CMOS logic gates, addressing PMOS and NMOS transistors design intricacies, series/parallel connections configurations, and practical insights into designing logic gates using CMOS networks.

Name:Analog Circuit CMOS Chip Design and Simulation Using Electric VLSI EDA Tool

Description:This module immerses participants in the schematic and layout design of fundamental components and circuits. It commences by introducing the fundamentals of stick diagrams, outlining the rules governing stick diagram and layout design, and providing a practical example for both stick and layout design. Subsequently, the module elucidates the installation process and step-by-step procedures for utilizing the Electric VLSI EDA tool. A comprehensive overview of the tool's built-in functions is provided, along with essential checks and waveform simulation. The module also covers the integration of LTspice with Electric VLSI EDA Tool, enhancing participants proficiency in design exploration. Furthermore, the module offers a concise introduction and procedural guidelines for designing schematic and layout representations of various electronic circuits, including PMOS, NMOS, CMOS inverter, Common Source Amplifier, Common Drain Amplifier, and a three-stage oscillator. Participants gain hands-on experience in representation, simulation, and 3D visualization of layout designs for these circuits. The procedures encompass Design Rule Checking (DRC) and Electrical Rule Checking (ERC), followed by NCC checks to ensure the practical implementation of the designs. This comprehensive approach ensures that participants not only grasp theoretical concepts but also acquire practical skills in the design and verification of electronic circuits using EDA tools.

Name:Digital Circuit CMOS Chip Design and Simulation Using Electric VLSI EDA Tool

Description:This module is designed to offer participants a deeper understanding of the schematic and layout design of various CMOS logic circuits. It guides participants through the process of creating a new cell in a predefined library, allowing them to choose between "schematic or layout" as the design approach. Emphasizing a systematic workflow, the module highlights that each design initiates with a schematic cell, subject to Design Rule Checking (DRC) at each step to assess the hierarchy of representations. The design is then simulated, and its characteristics are defined through waveform analysis. Participants will acquire the skills to craft the layout of schematic circuits, incorporating thorough checks such as DRC, Electrical Rule Checking (ERC), and Netlist-to-Component Connectivity (NCC) at the final stage. These checks ensure alignment between the designed layout and schematic, affirming the practical viability of the circuit. The module specifically covers the design of AND gate, OR gate, their complementary gates, XOR gate, and half adder circuits using the Electric VLSI EDA Tool and their characteristic verifications are done through LT spice software.

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