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所在平台: Coursera |
课程主页: https://www.coursera.org/learn/vlsi-cad-logic
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课程名称：VLSI CAD 第一部分：逻辑 概述：现代VLSI芯片极为复杂，包含数十亿个晶体管、数百万个用于计算和控制的逻辑门、大块内存以及由第三方设计的预定义功能块（称为“知识产权”或IP块）。在这个课程中，我们将探讨如何使用计算机辅助设计（CAD）工具来设计这些复杂的芯片。课程重点是创建特定应用集成电路（ASIC）或芯片系统（SoC）设计中使用的主要设计工具，尤其是布尔逻辑表示法，这使得合成和验证这些设计中的门级逻辑成为可能。该课程的目标是让学生了解这些工具的工作原理，包括它们的基本算法和数据结构。 推荐背景：具有编程经验（C、C++、Java、Python等）以及数据结构和算法的基础知识（特别是递归算法）。需理解基础数字设计，包括布尔代数、卡诺图、逻辑门和触发器、有限状态机设计。此外，要求具备大三或大四工程专业水平的线性代数和微积分知识。接触过本科水平的基础VLSI知识者将更为便利，但并非必要，课程会保持自足。 课程大纲： 1. 课程介绍：熟悉课程内容和学习环境，掌握课程所需的技术技能。 2. 计算布尔代数：介绍高级布尔代数数学概念，以实现“计算”方法。 3. 通过BDD和SAT的布尔表示：介绍用于进行大规模工业设计的重要表示技术。 4. 通过代数模型的2级逻辑合成和多级逻辑合成：从“表示”转向“合成”，进行逻辑优化。 5. 多级因子提取与无关项：学习如何提取复杂网络的共同因子，并利用无关项优化多级逻辑。 6. 期末考试：专注于完成最后的作业和期末考试。 通过本课程，学生将对VLSI设计的基本逻辑工具和算法有深入的理解，为后续的布局设计打下基础。
Name:Orientation
Description:In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.
Name:Computational Boolean Algebra
Description:In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to Boolean algebra.
Name:Boolean Representation via BDDs and SAT
Description:Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on industrial-scale designs.
Name:2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
Description:In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra.
Name:Multilevel Factor Extract and Don't Cares
Description:You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic.
Name:Final Exam
Description:There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.
A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level). Recommended Background Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.
