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所在平台: Coursera |
课程主页: https://www.coursera.org/learn/vlsi-cad-layout
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课程名称：VLSI CAD 第二部分：布局 课程概述：在开始本课程之前，请先完成VLSI CAD 第一部分：逻辑课程。现代VLSI芯片是一个极其复杂的系统，包含数十亿个晶体管和数百万个用于计算与控制的逻辑门、大量内存块，以及由第三方设计的预先设计的功能模块（称为“知识产权”或IP块）。设计这些复杂芯片的过程是如何进行的呢？答案是使用一系列计算机辅助设计（CAD）工具，从芯片的抽象描述开始，逐步细化至最终设计。本课程重点关注在设计特定应用集成电路（ASIC）或系统芯片（SoC）过程中使用的主要设计工具，尤其是使逻辑映射到布局的关键逻辑和几何表示。我们将讨论大规模逻辑网络的放置、布线及时序评估，旨在帮助学生理解这些工具的运作原理，包括其基本算法和数据结构。课程内容包括技术映射、时序分析、ASIC放置和布线等主题。 推荐背景：学习此课程之前，学员需具备编程经验（C、C++、Java、Python等）及基本的数据结构与算法知识（特别是递归算法）。同时需了解基本的数字设计知识，包括布尔代数、卡诺图、逻辑门与触发器、有限状态机设计，以及大三或大四工程水平的线性代数和微积分基础。此外，学员应具备初级RC线性电路的知识（相当于入门物理课程的水平）。 课程大纲： 1. **导论**：熟悉课程内容与学习环境，掌握课程所需的技术技能。 2. **ASIC放置**：讨论ASIC布局过程的概述，重点放置过程以及如何将数百万个逻辑门进行合理的布局。 3. **技术映射**：阐述从合成输出到实际逻辑门的转换过程，介绍涉及递归覆盖的优雅算法。 4. **ASIC布线**：讲解如何在芯片表面合理连接数百万个门，重点介绍古典而强大的迷宫布线技术。 5. **时序分析**：在完成上述步骤之后，介绍如何评估芯片的时序性能，包括逻辑门和大规模逻辑网络的延迟分析，以及静态时序分析（STA）的重要性。 6. **期末考试**：这一周没有新内容，重点完成最后的作业和期末考试。 通过以上内容，学生将深入了解VLSI设计中的布局和时序分析流程，掌握相关技术和工具。
Name:Orientation
Description:In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.
Name:ASIC Placement
Description:In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks.
Name:Technology Mapping
Description:Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD.
Name:ASIC Routing
Description:Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment.
Name:Timing Analysis
Description:You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.
Name:Final Exam
Description:There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.
You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).
