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所在平台: Coursera |
课程主页: https://www.coursera.org/learn/real-time-mission-critical-systems-design
课程评论：没有评论
课程名称：实时任务关键系统设计 课程概述：本课程可作为学术学分修读，属于科罗拉多大学博尔德分校电气工程硕士项目的ECEA 5317。完成本课程后，学习者将能够区分生命攸关的系统（任务关键）和提供可预测响应及服务质量的系统（可靠系统）。这一目标不仅通过对任务关键系统设计方法和模式的学习，还通过软实时系统的实施与硬实时系统进行比较来实现。学习者将学习验证方法，以确定满足任务关键和软实时要求的能力，从而能够正确评估实时系统中的风险、可靠性和故障影响。 课程结束时，学习者将能够将架构风格（循环执行、实时操作系统或嵌入式Linux）应用于任务关键系统、软实时系统或混合硬软实时系统的更详细设计，包括： ● 深入理解硬件/软件设备接口以及硬件抽象层（HAL, BSP）的资源视图 ● 不同实时硬件架构的设计权衡，包括单核、多核、混合FPGA、GP-GPU和DSP系统，特别强调多核 ● 任务关键嵌入式系统架构及其关键设计要素 ● 容错处理、内存和输入/输出概念 课程大纲： - 名称：实时系统的设备I/O接口和驱动程序 描述：本模块涵盖RTES软件与硬件接口，使用设备抽象和驱动程序接口以及系统扩展的内容。 - 名称：任务关键系统的容错内存和存储 描述：本模块涵盖关键算法的使用，如错误修正代码、冗余设备数组以及使用具有持久内存的闪存文件系统。 - 名称：解决实时系统中的性能和可靠性缺陷 描述：本模块涵盖服务软件的实现效率和优化方法，以确保计算能够在截止时间前完成。同时介绍了对应用程序及整个系统进行分析和跟踪的方法。 - 名称：硬、软实时系统的高可用性与高可靠性的区别 描述：本模块将容错和恢复方法与系统级故障检测、隔离和恢复的整体策略结合起来，涵盖针对故障模式和影响分析的设计，以及高可用性的冗余管理。 本课程为希望深入理解实时系统设计的学习者提供了全面的知识框架和实用技能。
Name:Device I/O interfaces and Drivers for Real-time Systems
Description:This module covers RTES software to hardware interface using device abstraction and driver interfaces as well as system scaling.
Name:Fault Tolerant Memory and Storage for Mission Critical Systems
Description:This module covers use of key algorithms such as error correct codes, redundant arrays of devices, and use of flash file systems with persistent memory.
Name:Solving performance and reliability defects in real-time systems
Description:Service software implementation efficiency and optimization methods are covered so that computations can be completed by deadlines. Methods of profiling and tracing applications as well as the whole system are covered.
Name:Difference between high availability and high reliability for hard and soft real-time systems
Description:This module integrates fault tolerant and recovery methods with overall strategies for system level fault detection, isolation and recovery. Design with consideration of failure modes and effects analysis is covered along with redundancy management for high availability.
This course can also be taken for academic credit as ECEA 5317, part of CU Boulder’s Master of Science in Electrical Engineering degree. Upon completion of this course the learner will know the difference between systems you can bet your life on (mission critical) and those which provide predictable response and quality of service (reliable). This will be achieved not only by study of design methods and patterns for mission critical systems, but also through implementation of soft real-time systems and comparison to hard real-time. Methods of verification to determine ability to meet mission critical as well as soft real-time requirements will be learned so that the learner can properly assess risk, reliability and impact of failure in real-time systems. At the end of this course learners will be able to apply an architectural style (cyclic executive, RTOS, or embedded Linux) to more detailed design of a mission critical system, a soft real-time system, or a mixed hard and soft real-time system, including: ● Thorough understanding of hardware/software device interfaces and resource view for hardware abstraction layers (HAL, BSP) ● Design trade-offs with different real-time hardware architectures including single core, multi-core, hybrid-FPGA, GP-GPU, and DSP systems, with emphasis on multi-core ● Mission critical embedded systems architecture and key design elements ● Fault tolerant processing, memory, and I/O concepts
