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所在平台: Coursera |
课程主页: https://www.coursera.org/learn/fpga-softcore-proccessors-ip
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课程名称：FPGA软核处理器与IP获取 概述：该课程将全面介绍FPGA设计中软处理器和知识产权（IP）的开发。您将学习软处理器的类型和能力，以及如何在FPGA中创建自己的软处理器，包括软处理器的硬件和软件设计。您还将学习如何向软处理器添加IP模块和自定义指令。在完成软处理器的创建后，您将了解如何使用仿真和内部逻辑分析仪验证设计。掌握创建和使用软处理器及IP的技能将对您大有裨益。 课程结构：该课程分为4个模块，每个模块约一个星期，历时4周。每个模块包括1至2小时的视频讲座、阅读作业、讨论提示以及模块结束评估。 课程大纲： 1. **软核处理器开发流程** 本模块介绍了软处理器的概念，特别是软处理器的硬件设计。内容涵盖Xilinx、Altera、Microsemi和Lattice等公司提供的各种软处理器，并深入分析Altera的Nios II软处理器。介绍了使用软处理器的好处，以防止技术过时并提供灵活性。本模块还指导您使用Altera系统设计工具Qsys设计Nios II处理器的硬件，并演示了在Nios II中设计自定义指令，以展示FPGA中软处理器的灵活性。 2. **为软核处理器编写软件** 本模块深入探讨软处理器的开发流程，包括为软处理器开发软件所需的工具。介绍了基于Eclipse的Nios II软件开发IDE，并展示如何使用Qsys设计的输出建立处理器的板级支持包（BSP），以适应处理器硬件设计的变化。演示了如何使用BSP编辑器通过编程控制寄存器来配置处理器。最后，呈现了如何使用第1模块中开发的自定义指令，包括使用软件宏完成自定义指令的实现。 3. **IP获取与集成** 现代FPGA设计不再仅仅集中于HDL模块设计，而是更多依赖IP核心的获取与使用。本模块将介绍包括Intel Altera、Xilinx、Microchip Microsemi和Lattice在内的主要供应商提供的IP核心。您将学习如何查找、获取和使用这些核心。 4. **ModelSim与验证仿真介绍** 随着FPGA设计日益复杂，创建无误设计的挑战日益加剧。掌握验证设计正确性所需工具的能力变得越来越重要。在之前的课程中介绍了仿真，本模块将深入研究ModelSim的仿真，并通过一些实例进行演示。这将展示仿真在验证和调试中的实用性。本模块还将详细描述模拟器的工作原理及其如何通过使用增量延迟实现并发性。最后，介绍内部逻辑分析仪SignalTap II作为调试过程的最终步骤。 完成本课程后，您将具备创建和使用软处理器及IP的实用技能，对从事FPGA设计的专业人员来说，这是一项非常有价值的能力。
Name:Softcore Processor Development Flow
Description:This module introduces the concept of a soft processor in general, and of hardware design for the soft processor in particular. It presents an overview of soft processors, describing all the different kinds that are available from Xilinx, Altera, Microsemi, and Lattice and then goes into depth about the Nios II soft processor from Altera. The benefits of using soft processors to prevent obsolescence and provide flexibility are explained. The content guides you through a hardware design of the Nios II processor using Qsys, the Altera system design tool. Lastly, design of a custom instruction in the Nios II is presented, showing the versatility of the soft processor in an FPGA.
Name:Writing Software for Softcore Processors
Description:This module delves further into the development of soft processors, It describes the soft processor development flow in more detail, including the tools needed to develop software for the soft processor. It then introduces the Eclipse-based IDE for Nios II software development, and then shows how the output of the Qsys design is used to establish a Board Support Package (BSP) for the processor, which is necessary because the processor hardware design can be changed and the BSP software library must support any changes. Use of the BSP editor to configure the processor by programming control registers is demonstrated. Finally, the use of the custom instruction developed in Module 1 is presented, including the use of software macros to complete the implementation of the custom instruction.
Name:IP Acquisition and Integration
Description:Modern FPGA design is no longer centered on HDL module design as it is on acquisition and use of IP Cores. In this Module we will introduce IP cores including offerings from all the major vendors, Intel Altera, Xilinx, Microchip Microsemi, and Lattice. You will learn how to find, acquire, and use these cores.
Name:Introducing ModelSim and Simulation for Verification
Description:As we work on more complex FPGA designs, the challenges to create an error-free design mount exponentially. Having a good grasp of the tools needed to verify correctness of design has become more and more important. After introducing simulation in previous sessions, in this module we will examine simulation with ModelSim in more depth by working through some examples. This will show the utility of simulation for verification and debugging. This module will also describe in some detail how the simulator works and how it achieves concurrency through the use of delta delays. As a final step in the debugging process, the internal logic analyzer SignalTap II is introduced.
This course will introduce you to all aspects of development of Soft Processors and Intellectual Property (IP) in FPGA design. You will learn the extent of Soft Processor types and capabilities, how to make your own Soft Processor in and FPGA, including how to design the hardware and the software for a Soft Processor. You will learn how to add IP blocks and custom instructions to your Soft Processor. After the Soft Processor is made, you learn how to verify the design using simulation and an internal logic analyzer. Once complete you will know how to create and use Soft Processors and IP, a very useful skill. This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or two of video lectures, reading assignments, discussion prompts, and an end of module assessment.
