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所在平台: Coursera |
课程主页: https://www.coursera.org/learn/fpga-hardware-description-languages
课程评论：没有评论
课程名称：FPGA设计的硬件描述语言 课程概述：本课程可作为CU Boulder电气工程硕士学位的学术学分课程 ECEA 5361。硬件描述语言与逻辑设计课程使学生能够使用VHDL和Verilog这两种最广泛应用于FPGA设计的方法来设计电路。通过自然学习过程，使学习这些语言变得轻松。课程从简单的初步示例开始，接着讲解语言规则和语法，然后展示更复杂的示例，最后使用测试台仿真验证设计的正确性。讲座通过大量编程示例问题进行巩固，帮助学生掌握这些语言。在完成此课程后，学生将具备这两种语言的基本熟练程度，更重要的是，拥有继续自学和深入掌握Verilog与VHDL的知识基础。 课程大纲： 1. **VHDL基础** - 描述：本模块介绍VHDL语言的基础知识，用于逻辑设计。讨论VHDL在FPGA和ASIC设计中的作用，并展示VHDL在FPGA设计流程中的位置。通过一个简单示例（4位比较器）作为语言的入门，讲解VHDL的规则和语法、语句、标识符和关键字。最后，展示如何使用ModelSim仿真软件工具进行VHDL电路设计的测试。通过编程作业来提升技能和巩固概念。 2. **VHDL逻辑设计技术** - 描述：本模块进一步探讨使用VHDL进行逻辑设计，提供多种组合逻辑和时序逻辑电路示例（包括触发器、计数器、寄存器、内存、三态缓冲器和有限状态机）。讲解和演示层次化设计和模块化设计技术，并描述如何创建测试台作为设计验证的手段。学生们通过编程作业有充分的机会练习和提高设计技术。 3. **Verilog基础** - 描述：本模块介绍Verilog语言的基础知识，用于逻辑设计。讨论Verilog作为FPGA和ASIC逻辑设计的输入方法，包括Verilog的发展历史。使用4位比较器作为语言的入门示例，讲解Verilog的规则和语法、语句、运算符及关键字。最后，展示如何使用ModelSim进行Verilog电路设计的仿真测试。通过编程作业来提升技能和巩固所学概念。 4. **Verilog和System Verilog设计技术** - 描述：本模块进一步探讨使用Verilog进行逻辑设计，提供多种组合逻辑和时序逻辑电路示例（包括触发器、计数器、寄存器、内存、三态缓冲器和有限状态机）。讲解和演示层次化设计和模块化设计技术，并描述如何创建测试台作为设计验证的手段。学生们通过编程作业有充分的机会练习和提高设计技术。
Name:Basics of VHDL
Description:This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
Name:VHDL Logic Design Techniques
Description:In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
Name:Basics of Verilog
Description:This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
Name:Verilog and System Verilog Design Techniques
Description:In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
