FPGA Capstone: Building FPGA Projects

所在平台: Coursera

课程主页: https://www.coursera.org/learn/capstone-fpga-design

课程评论:没有评论

第一个写评论        关注课程

课程简介

课程名称:FPGA 终极项目:构建 FPGA 项目 课程概述:本课程旨在提供实践性的 FPGA 设计经验,应用您迄今为止掌握的所有概念和技能。学员需购买 DE10-Lite 开发套件,并使用 FPGA 设计工具 Quartus Prime 和 System Builder 设置和测试 MAX10 DE10-Lite 板。课程内容包括: - 设计并测试一个二进制编码十进制加法器(BCD 加法器)。 - 设计并测试一个脉宽调制(PWM)电路,并通过仿真进行验证。 - 设计并测试一个模拟到数字转换器(ADC)电路,利用 Quartus Prime 内置工具验证电路设计。 - 使用 Qsys(平台设计器)为 NIOS II 软处理器创建硬件,包括多个接口,并将该设计实例化到 DE10-Lite 顶层 HDL 文件中。 - 使用 Quartus Prime 编译完成的硬件。 - 在 Quartus Prime 设计流程及 NIOS II 软件构建工具(SBT for Eclipse)中增强和测试现有设计。 - 使用 Qsys 和 SBT 为 NIOS II 软处理器创建软件,包括多个接口,并编译完成的软件。 - 使用 Quartus Prime 为 DE10-Lite 开发套件编程 FPGA 硬件配置和软件代码。 - 在实验日志中记录所有观察结果,并提交项目文件与实验日志进行评分。 课程结构包括四个模块,预计每周一个模块,共四周。每个模块将包含一小时或更少的视频讲座,此外还有阅读作业、讨论提示和项目作业,涉及在 FPGA 中创建硬件和/或软件。 课程大纲: 1. **动手实践:Altera MAX10 硬件设置** - 目标:设置并测试 MAX10 板,设计并测试 BCD 加法器,记录观察,提交项目文件进行评分。 2. **开发混合信号系统** - 目标:构建一个使用 ADC 输入和 PWM 输出的硬件系统,设计和测试 PWM 电路和 ADC 电路,记录观察,提交项目文件进行评分。 3. **创建一个带 NIOS II 的系统单芯片** - 目标:创建 NIOS II 软处理器的硬件,实例化到顶层 DE10-Lite HDL 文件,记录观察,提交项目文件进行评分。 4. **为系统单芯片开发软件** - 目标:为 NIOS II 软处理器构建软件,测试新的嵌入式系统,记录观察,提交项目文件进行评分。 完成本课程将使您掌握在 FPGA 设计和实现嵌入式系统中的关键技能。

课程大纲

Name:Hands on: Altera MAX10 Hardware Setup

Description:In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA. In this module you will  Setup and test the MAX10 board using the FPGA design tool Quartus Prime and the System Builder.  Design and test a Binary Coded Decimal Adder Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will help prepare you for the work to be done in the modules that follow.

Name:Develop a Mixed Signal System

Description:The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument. In this module you will  Create a working design, using most aspects of the Quartus Prime Design Flow.  Design and test a PWM Circuit, with verification by simulation.  Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will help prepare you for the work to be done in the modules that follow.

Name:Create a System on a Chip with NIOS II

Description:The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit. In this module you will  Create a working design, using most aspects of the Quartus Prime Design Flow.  Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder). Instantiate this design into a top-level DE10-Lite HDL file.  Compile your completed hardware using Quartus Prime.  Record all your observations in a lab notebook.  Submit your project files and lab notebook for grading. Completing this module will provide a platform for the work to be done in the module that follows.

Name:Software for a System on a Chip

Description:The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well. In this module you will  Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.  Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder) and the SBT.  Compile your completed software using the SBT.  Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. You will then test your new embedded system.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will finish your work for this course.

课程评论(0条)

课程详情

This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now. You will need to purchase a DE10-Lite development kit. You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder. You will: Design and test a Binary Coded Decimal Adder. Design and test a PWM Circuit, with verification by simulation. Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design. Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file. Compile your completed hardware using Quartus Prime. Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse. Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT. Compile your completed software using the SBT. Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. Record all your observations in a lab notebook pdf. Submit your project files and lab notebook for grading. This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

课程标签

0人关注该课程

主题相关的课程