VLSI CAD: Logic to Layout
持续时间: 10 weeks
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A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus is on the key representations that make it possible to synthesize, and to verify, these designs, as they move from logic to layout.
Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. You should be taking this course if (1) you are interested in building VLSI design tools; (2) you are interested in designing VLSI chips, and you want to know why the tools do what they do; (3) you just like cool algorithms, that work on big cool problems that involve bits, and gates, and geometry, and graphs, and matrices, and time, and...
Topics covered will include: Computational boolean algebra; logic verification; logic synthesis (2-level and multi-level); technology mapping; timing analysis; ASIC placement and routing.